Input terminals of conventional digital circuits are designed to normally receive a relatively low voltage level range of input signals of less than seven volts to indicate binary logic values of "1" and "0" or "high" and "low". The low voltage level input signals normally range from -1.0 volts to 6.5 volts in typical complementary metal oxide semiconductor (CMOS) integrated circuits.
Because the number of terminal pins on an integrated circuit is limited, it is sometimes desirable to connect a common or single terminal to be different circuits, particularly if the two circuits are intended to be operated during different time intervals. The activation of the less used or special circuit is frequently accomplished by the application of a high voltage level signal significantly above the low voltage level. The special high voltage level, referred to herein as V.sub.act, is used to activate the special mode circuit within the device. For example, CMOS random access memory integrated circuit devices have special test mode circuits combined on the device for testing the memory circuit. The special test mode circuits can be activated by presenting the special high voltage level on an input pin normally used for transmitting data to the memory circuit. The special high voltage level is significantly greater than the low voltage level normally associated with "high" and "low" binary logic values within the circuit and should not be confused with the "high" voltage which corresponds to a logic "1". The special high voltage typically ranges from 10 to 25 volts, depending on the particular circuit in which it is used.
FIG. 1 shows a typical arrangement of a CMOS semiconductor integrated circuit device 10 including an input terminal 12 that is intended to receive both a low voltage level signal and a special high voltage level signal. Operational circuits 18, within integrated circuit device 10, normally operate on low voltage level signals. Operational circuits 18 are connected to input terminal 12 through input line 22 and are adapted to receive normal low voltage level binary logic signals from input terminal 12. One of the operational circuits 18 is identified as a special mode circuit 20 because it, when activated, initiates a special mode or function, such as a test mode.
In integrated circuits using metal oxide semiconductor field effect transistor (MOSFET) technology, input terminals are usually connected to the gate of a MOSFET. While such a gate is typically capable of withstanding a special high voltage level signal, it is incapable, under normal biasing levels, of distinguishing between low level signals used for binary logic state transfer ("1" and "0") and a special high voltage level signal used to activate a special mode circuit. Therefore, a special activation circuit is required to detect a special high voltage level signal and to activate the special mode circuit only when such a high voltage level signal is applied to the input terminal.
Accordingly, integrated circuit 10 includes a special mode activation circuit 14 for detecting a special high voltage level signal and for activating special mode circuit 20 when such a signal is present at input terminal 12. Special mode activation circuit 14 is connected directly to input terminal 12 through input line 22, and activates the special mode circuit 20 through activation line 24.
In operation, special mode activation circuit 14 maintains the special mode circuit 20 deactivated when the input ternimal is at the low voltage level normally associated with binary logic values processed by operational circuits 18. Special mode activation circuit 14 activates special mode circuit 20 only when the input signal is changed to the special high voltage level.
Ideally, special mode activation circuit 14 should have no electrical effect on input line 22; i.e., it should present a very high impedance at its input. In addition, the voltage required at input terminal 12 to activate special mode circuit 20 (V.sub.act) should be significantly above the low voltage level normally associated with binary logic values, and should be constant regardless of semiconductor process variations.
FIG. 2 shows a prior art special mode activation circuit 40. Circuit 40 comprises a p-channel MOSFET 42 and an n-channel MOSFET 44. The gates of transistors 42 and 44 are connected together and to a positive reference voltage, V.sub.dd. The drains of transistors 42 and 44 are connected together to the input of a voltage inverter 46. The output of voltage inverter 46 is connected through activation line 24 to the special mode circuit 20 (FIG. 1). The source of transistor 14 is connected to a negative reference voltage, V.sub.ss, or ground, and the source of transistor 42 is connected to input terminal 12 (FIG. 1) through input line 22. The voltage at input line 22 is referred to as V.sub.in for convenience.
Transistor 44, with its gate connected to V.sub.dd and its source connected to ground, will conduct at all times, pulling the input of inverter 46 low. However, p-channel transistor 42 will also begin to conduct when V.sub.in exceeds V.sub.dd by more than the threshold voltage V.sub.T of transistor 42.
The operational and dimensional parameters of transistors 42 and 44 can be selected for differing responses to V.sub.in. For instance, transistor 44 can be made much smaller than transistor 42, with a resulting relatively low conductance. In this case, transistor 44 will weakly pull the input of inverter 46 to ground. When transistor 42 begins to conduct, it will quickly, due to its greater conductance, pull the input of inverter 46 to V.sub.in. Thus, the input of inverter 46 will be abruptly changed from a low to a high as V.sub.in exceeds V.sub.dd +V.sub.T, and inverter 46 will, as a result, activate special mode circuit 20.
If, on the other hand, transistors 42 and 44 are constructed to have more nearly equal conductances, they will act as a voltage divider as transistor 42 begins to conduct. Thus, the input of inverter 46 will change gradually from a low to a high, eventually reaching a threshold at which inverter 46 will switch its output, activation line 24, to activate the special mode circuit 20.
Unfortunately, special mode activation circuit 40 does not always present a high impedance to input line 22. Specifically, circuit 40 requires current from input terminal 12 whenever V.sub.in exceeds V.sub.dd +V.sub.T. In addition, the voltage at which special mode circuit 20 will be activated will vary unpredictably by several volts depending on the supply voltage of inverter 46. This is because the threshold at which inverter 46 will switch its output to activate special mode circuit 20 will vary within wide limits as the supply voltage of inverter 46 changes. A further problem with the circuit of FIG. 2 is that, regardless of trnsistor sizes, circuit 40 is particularly susceptible to latchup if V.sub.in rises quickly from a low voltage level signal to the special high voltage level signal. Latchup is a common and well-known problem in CMOS circuits.
Another prior art special mode activation circuit 50 is shown in FIG. 2 that comprises a series of n-channel MOSFETs 52, connected to function as diodes, an n-channel MOSFET 54, and a voltage inverter 56. Each of diode-connected transistors 52 has its gate connected to its drain so that it will conduct only when the voltage of the drain with respect to the source exceeds the threshold voltage V.sub.T of such transistor 52. Each transistor 52 thus functions as a diode, preventing reverse current and dropping an incremental voltage equal to V.sub.T. Transistors 52 are connected in series, with the gate and drain of the first transistor 52 connected to V.sub.in and the source of the last transistor 52 connected to the drain of transistor 24 and to the input of inverter 56. The output of inverter 56 is connected through activation line 24 to special mode circuit 20 (FIG. 1).
Transistor 54 is coupled between the input of inverter 56 and ground to normally hold the input of the inverter "low." The transistor has a gate connected to V.sub.dd and a source connected to a negative reference voltage, V.sub.ss, or ground. However, the structural and electrical parameters of transistor 54 are selected to provide a relatively low conductance. Therefore, transistor 54 functions much like a resistor, weakly pulling the input of inverter 56 to ground.
In operation, if V.sub.in is less than the combined threshold voltages V.sub.T of transistors 52, it will not be conducted to the input of inverter 56. Thus, in effect, a constant voltage is subtracted from V.sub.in, depending on the number of diode-connected transistors 52. Weak transistor 54 has little effect on the voltage at the input of inverter 56 once transistors 22 begin conducting and a reduced voltage (with respect to V.sub.in) is therefore presented to the input of inverter 56. Inverter 56 will switch activation line 24 to activate special mode circuit 20 as its input reaches the inverter threshold.
Again, however, circuit 50 does not present a high impedance to input line 22. Special mode activation circuit 50 requires current from input line 22 whenever V.sub.in exceeds the combined threshold voltages of transistors 52, regardless of whether V.sub.in has exceeded the voltage required to actually activate special mode circuit 20. Also, like special mode activation circuit 40 of FIG. 2, the inverter threshold is unpredictably dependent upon the supply voltage.
Accordingly, a need remains for a special mode activation circuit which may be used in CMOS integrated circuits to activate a special mode circuit when the voltage at an input terminal exceeds an arbitrarily selected value. Such a circuit should require little or no current from the input terminal until the special high voltage level is reached, should be insensitive to process variations, and should be reasonably immune from induced CMOS latchup.